1. Field of the Invention
The present invention relates to semiconductor wafer deposition and planarization and, more particularly, to apparatuses and techniques for more effectively depositing thin films using localized deposition and for enabling localized planarization.
2. Description of the Related Art
Electroplating is a well-established deposition technology. In the semiconductor fabrication arts, electroplating is typically performed in a single-wafer processor, with the wafer immersed in an electrolyte. During electroplating, the wafer is typically held in a wafer holder, at a negative, or ground potential, with respect to a positively charged plate (also immersed in the electrolyte) which acts as an anode. To form a copper layer, for example, the electrolyte is typically between about 0.3M and about 0.85M CuSO4, pH between about 0 and about 2 (adjusted by H2SO4), with trace levels (in ppm concentrations) of proprietary organic additives as well as Cl− to enhance the deposit quality. During the plating process the wafer is typically rotated to facilitate uniform plating. After a sufficient film thickness has been achieved during the plating process, the wafer is moved from the plating chamber to another chamber where it is rinsed in de-ionized (DI) water, to remove residual electrolyte from the wafer surface. Next the wafer is subjected to additional wet processing, to remove unwanted copper from the backside and bevel edge, and then another DI water rinse removes wet processing chemical residues. Then the wafer is dried and annealed before it is ready for the chemical mechanical planarization (CMP) operation.
Unlike vacuum processing of wafers, each “wet” processing step during wafer processing today is followed by an overhead step of a DI water rinse. Due to electrolyte dilution concerns and increased hardware design complexity, DI water rinsing is typically not done within the plating chamber. Today, approximately fifty percent of the wet processing stations on a wafer plating tool are dedicated to plating, having a significant negative impact on wafer throughput and increasing processing cost. In addition, to enable direct copper plating on the barrier layer, minimizing time between surface activation and plating is critical. The additional time, to rinse after surface activation and to transport the wafer to the plating module, significantly limits the effectiveness of the surface activation step. What is needed is a way of eliminating DI water rinses between wet processing steps.
During the plating process, the wafer acts as a cathode, which requires that the power supply be electrically connected to the wafer. Typically, numerous discrete contacts on the wafer holder connect the wafer holder electrically to the edge of the wafer. The current utilized to electroplate the wafers is provided through these contacts. Plating current must be evenly distributed around the perimeter of the wafer to provide uniform deposition. Maintaining consistent contact resistance with the wafer, through the resistive seed layer, is critical for uniform deposition. Therefore, in an effort to provide uniform deposition, cleanliness of the contacts is preferred. In some cases, cleaning of the contacts requires additional steps further limiting the productivity of the plating operation.
Another challenge in copper electroplating is a bipolar effect, observed when the contact resistance is very high. This effect induces etching of the copper seed layer directly under the contacts, thereby severing as the electrical contact between the wafer and the power supply during electroplating. Prior art approaches have attempted to resolve this issue by sealing the contacts from the electrolyte, thereby preventing plating on the contacts and eliminating the bipolar effect. Unfortunately, seals are not perfect and contacts become contaminated and current distribution in the contacts along the wafer periphery results in non-uniform plating. Consequently, contact resistance must be controlled by some other way of active monitoring during the plating process.
Additional adverse physical challenges occur when applying the contacts to the surface of the wafer. While the contacts are typically placed in the exclusion area (e.g., a 1-3 mm outer region of the wafer) of the wafer, some amount of force must be applied to maintain consistent electrical contact with the wafer. Application of such force can, in some cases cause defects on the wafer due to mechanical stresses on certain materials, such as porous low-k dielectric films.
As feature dimensions on semiconductor wafers continue to shrink, the copper seed layer thickness is also expected to decrease, from approximately 1000 angstroms today to less than about 400 angstroms. Thickness reduction of the seed layer is necessary to ensure a reasonable sized opening at the top of the features so as to enable void free gap fill during the copper electroplating process. Since the role of the seed layer is to distribute the plating current over the entire wafer during electroplating, a thinner more resistive seed layer introduces a significant challenge in chambers designed for uniform plating near contacts on the wafer periphery. Known as the terminal effect, this effect is more pronounced on larger wafers, such as today's 300 mm wafers.
What is needed therefore, is an electroplating system that limits rinsing processes and provides sufficient electrical contact without applying excessive surface force while producing uniform electroplating on wafers with little or no seed layer.